INTERCONNECT VIA WITH INDUCED ASYMMETRIC PROFILE

Abstract: techniques are provided herein for forming a via with an asymmetrically flared profile within the interconnect region over semiconductor devices. in some examples, a via within the interconnect layer has a greater critical dimension (cd), or top surface width, along a first direction (e.g., along an x-axis) than it has along a second direction orthogonal to the first direction (e.g., along a y-axis). the bottom surface of the via may have substantially the same width along both the first and second directions, such that the width of the via tapers or steps inward between the top surface width along the first direction and the bottom surface width along the first direction. there is little to no tapering or step of the via between the top surface width along the second direction and the bottom surface width along the second direction.

Inventor(s): Angelo W. Kandas, Codi A. Sanders, Mansi Seth, Jessica A. Parker, Ameen Sayal, Mark Koeper, Nicholas J. Kybert

CPC Classification: H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (use of semiconductor devices for measuring ; resistors in general ; magnets, inductors or transformers ; capacitors in general ; electrolytic devices ; batteries or accumulators ; waveguides, resonators or lines of the waveguide type ; line connectors or current collectors ; stimulated-emission devices ; electromechanical resonators ; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers ; electric light sources in general ; printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components ; use of semiconductor devices in circuits having a particular application, see the subclass for the application))

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