CHIP INTEGRATION INTO CAVITIES OF A HOST WAFER USING LATERAL DIELECTRIC MATERIAL BONDING

Abstract: an electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. a lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Inventor(s): Florian Herrault, Isaac Rivera, Daniel S. Green, James F. Buckwalter

CPC Classification: H01L23/3114 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (use of semiconductor devices for measuring ; resistors in general ; magnets, inductors or transformers ; capacitors in general ; electrolytic devices ; batteries or accumulators ; waveguides, resonators or lines of the waveguide type ; line connectors or current collectors ; stimulated-emission devices ; electromechanical resonators ; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers ; electric light sources in general ; printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components ; use of semiconductor devices in circuits having a particular application, see the subclass for the application))

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