MEMORY BIST CIRCUIT AND METHOD

Abstract: an electronic circuit includes: a memory including a data input, an address input, a command input, and a data output; a register having a data input coupled to the data output of the memory; a comparator circuit having a first data input coupled to the data output of the memory, and a second data input coupled to a data output of the register; an inverter circuit having a data input coupled to the data output of the register, and a data output coupled to the data input of the memory; and a controller having a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to a data output of the comparator circuit, where the controller is configured to determine whether the memory has a fault based on the fault input of the controller.

Inventor(s): Devanathan Varadarajan

CPC Classification: G11C29/1201 (STATIC STORES (semiconductor memory devices ))

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