DUAL RAIL MEMORY DEVICE

Abstract: a memory device has a memory cell operated in a first power domain having a first voltage level. a memory word line is connected to the memory cell, and a memory bit line is connected to the memory cell. a word line decoder circuit is operated in the first power domain, and a word line driver circuit is configured to receive a row address signal from the word line decoder circuit and output a word line enable signal to the memory word line. an io circuit is connected to the memory bit line, and the io circuit is operated in a second power domain having a second voltage level lower than the first voltage level. a tracking word line is connected to a tracking cell, and the tracking word line is configured to output a tracking cell enable signal in the first power domain. a tracking bit line is connected to the tracking cell, and the tracking bit line is configured to output a trigger signal in the first power domain to the io circuit.

Inventor(s): YEN-CHI CHOU, SHAO HSUAN HSU, TZU CHUN LIN, CHIEN-YU HUANG, CHENG HUNG LEE, HUNG-JEN LIAO

CPC Classification: G11C11/418 (forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger)

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