SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Abstract: a method of operating a semiconductor memory device includes: providing nbti information including row addresses of nbti vulnerable cells among the plurality of memory cells such that a decrease in a threshold voltage of the cell transistor due to application of the normal turn-off voltage about the nbti vulnerable cells is greater than a reference decrease value; providing pbti information including row addresses of pbti vulnerable cells among the plurality of memory cells such that an increase in the threshold voltage of the cell transistor due to application of the normal turn-on voltage about the pbti vulnerable cells is greater than a reference increase value; increase the threshold voltage of the nbti vulnerable cells by performing an nbti compensation operation based on the nbti information; and decrease the threshold voltage of the pbti vulnerable cells by performing a pbti compensation operation based on the pbti information.

Inventor(s): Sangyun KIM, Younghun SEO, Kyuchang KANG, Incheol NAM, Jaejoon SONG

CPC Classification: G11C11/40626 (STATIC STORES (semiconductor memory devices ))

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