CLOCK GENERATION CIRCUIT AND MEMORY

Abstract: embodiments of the present disclosure provide a clock generation circuit and a memory. the ith clock generation sub-circuit is configured to: perform sampling processing and latching processing on the ith register input signal based on an inverted clock signal, to generate the ith register signal; and perform first logic processing on the ith register signal and a delayed clock signal, to generate the ith target clock signal. the jth clock generation sub-circuit is configured to: perform sampling processing and latching processing on the (j-1)th register signal based on a preset clock signal, to generate the jth register signal; and perform second logic processing on the jth register signal and the delayed clock signal, to generate the jth target clock signal.

Inventor(s): Jun Yang, Zequn Huang

CPC Classification: G11C7/1066 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers)

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