SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME

Abstract: a semiconductor memory device includes an external resistor in a board, and a plurality of memory dies mounted on the board and that are designated as a master die and slave dies. the memory dies are commonly connected to the external resistor. the master die performs a first impedance calibration operation and outputs a first done signal indicating completion of the first impedance calibration operation to the slave dies through a first impedance pad. each of the slave dies includes a second impedance pad, and receives the first done signal through the second impedance pad, generates an identification signal based on the first done signal, performs a second impedance calibration operation sequentially with respect to the other slave dies based on the identification signal, and outputs a second done signal indicating completion of the second impedance calibration operation through the second impedance pad.

Inventor(s): Junbae KIM, Geunhee LEE, Yoochang SUNG

CPC Classification: G11C7/1063 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers)

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