Interconnect Structure For An Array Of Multi-Threaded Dynamic Random Access Memory Systems

Abstract: an arrayed processor system having an array of stacked mtdram processor systems. each stacked mtdram processor system includes a controller chip having a plurality of processor blocks arranged in an array, and a plurality of dram chips. each dram chip includes a plurality of independent dram unit cells arranged in an array, wherein each of the processor blocks of the controller chip is coupled to a corresponding dram unit cell in each of the dram chips. the arrayed processor system further includes communication control chips coupled to the stacked mtdram processor systems, power management chips coupled to the communication control chips and the stacked mtdram processor systems, and high-speed communication links coupled to the communication control chips. the various elements of the arrayed processor system are mounted on, and are interconnected by, an interconnect structure that includes a silicon substrate with a plurality of patterned metal interconnect layers formed thereon.

Inventor(s): Richard S. Roy

CPC Classification: G11C5/06 (STATIC STORES (semiconductor memory devices ))

Search for rejections for patent application number 20250218468