20250217561. Semiconductor Test Structure (Intel)
SEMICONDUCTOR TEST STRUCTURE GENERATION BASED ON LITHOGRAPHIC SIMULATION
Abstract: a method comprising accessing, by at least one computing system, a plurality of layout blocks comprising a plurality of design patterns for an interconnect layer and identifications of lithography risk sites of the plurality of design patterns, the lithography risk sites corresponding to violations of constraint based checks for simulated physical patterns corresponding to the plurality of design patterns; and generating, by the at least one computing system, a layout comprising the plurality of layout blocks and at least one routing path that is coupled to a subset of the plurality of design patterns having lithography risk sites.
Inventor(s): Brian Hendrik Miller, Daniel L. Stahlke, Jonah Mckenzie, Chunyong He, Pavan Kumar Vaitheeswaran, Muhammad Muqarrab Bashir, Bikram Baidya, Allan Gu
CPC Classification: G06F30/31 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models ))
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- Patent Applications
- Intel Corporation
- CPC G06F30/31
- Brian Hendrik Miller of Hillsboro OR US
- Daniel L. Stahlke of Hillsboro OR US
- Jonah Mckenzie of Portland OR US
- Chunyong He of Portland OR US
- Pavan Kumar Vaitheeswaran of Hillsboro OR US
- Muhammad Muqarrab Bashir of Portland OR US
- Bikram Baidya of Portland OR US
- Allan Gu of Portland OR US