Adaptive Configuration of Address Translation Cache

Abstract: a peripheral device includes a bus interface and an address translation service (ats) controller. the bus interface is to communicate over a peripheral bus. the ats controller is to communicate over the peripheral bus, including sending address translation requests and receiving address translations in response to the address translation requests, to cache at least some of the address translations in one or more address translation caches (atcs), to estimate one or more statistical properties of the received address translations, and to configure the one or more atcs based on the one or more statistical properties.

Inventor(s): Gal Shalom, Daniel Marcovitch, Ran Avraham Koren, Amir Sharaffy, Shay Aisman, Ariel Shahar

CPC Classification: G06F12/1027 (using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB])

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