FAULT TOLERANT ARCHITECTURE

Abstract: a system/process provides fault tolerance to an integrated component system which integrates core components of a transaction processing system into a single processing platform, i.e., a single server, enabling elimination of the network interconnects and associated latencies introduced thereby in favor of much faster interconnects, such as inter-process communication and shared memory communication messaging, where a failure of any one component necessitates failing over the entire system to a backup thereof.

Inventor(s): Dileep Chakravarthi Konduru, Priteshkumar Soni, Arkadiusz Koziol, Matthew Coffey, Nagesh Reddy, Satya Kamineni, Madhur Sirohi

CPC Classification: G06F11/2005 ({using redundant communication controllers})

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