TRANSACTIONAL TIMEOUTS FOR MANAGING CRITICAL DOMAINS

Abstract: processing systems and associated methods are provided for managing tasks and handling errors based on criticality levels assigned to individual processing circuitry blocks. the system includes a plurality of processing circuitry blocks, each assigned a level of criticality by a critical domain manager, such that errors arising in relation to these blocks are handled in accordance with their assigned level of criticality. the system features timers assigned to tasks initiated by the processing circuitry blocks, with timeout durations determined by the criticality levels respectively assigned to the processing circuitry blocks and tasks initiated by them. upon timeout expiration without task completion, various error handling procedures are selected and executed based on the assigned criticality levels.

Inventor(s): Balatripura S. Chavali, Kaushal Amolak Sanghai, Uma Sankara Rao Balla, Carl Kittredge Wakeland

CPC Classification: G06F11/0757 (Responding to the occurrence of a fault, e.g. fault tolerance)

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