Translation Barrier Instruction

Abstract: an apparatus may include a processor circuit that may be configured to execute a translation barrier instruction. to execute the translation barrier instruction, the processor circuit may be configured to prevent, until after the translation barrier instruction completes, address translations for instructions that occur subsequent to the translation barrier instruction in program order. the processor circuit may be further configured to complete the translation barrier instruction based on finishing all address translations for instructions that occur prior to the translation barrier instruction in program order.

Inventor(s): Jeff Gonion

CPC Classification: G06F9/522 (Program synchronisation; Mutual exclusion, e.g. by means of semaphores)

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