REDUCING CAPACITANCE IN SEMICONDUCTOR DEVICES

Abstract: methods of forming air gaps in hole and trench structures using plasma enhanced atomic layer deposition (peald) are disclosed. the methods may be used to form buried voids, i.e., voids for which the top is below the top of the adjacent features. in some embodiments, the methods are to reduce intra-level capacitance in semiconductor devices.

Inventor(s): Ian John CURTIN, Douglas Walter AGNEW, Zhe GUI, Tobias PEISSKER, Bart J. VAN SCHRAVENDIJK

CPC Classification: C23C16/045 (COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion ; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. , ; metallising of glass ; metallising mortars, concrete, artificial stone, ceramics or natural stone ; enamelling of, or applying a vitreous layer to, metals ; treating metal surfaces or coating of metals by electrolysis or electrophoresis ; single-crystal film growth ; by metallising textiles ; decorating textiles by locally metallising ))

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