CORRECTING RULE VIOLATIONS IN A LAYOUT

Abstract: some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. this pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). this method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. in some embodiments, the layout is a mask layout used to manufacture the ic, while in other embodiments, the layout is a design layout used to design the ic (e.g., a layout used during the physical design process).

Inventor(s): Mariusz A. Niewczas, Yefim G. Belenky, Abhishek Shendre, Michael Pomerantsev, Akira Fujimura

CPC Classification: G06F30/398 (Circuit design at the physical level (physical level design for reconfigurable circuits ))

Search for rejections for patent application number 20250190674