SYSTEM AND METHOD FOR IMPROVING DYNAMIC VOLTAGE DROP STIMULUS COVERAGE IN SEMICONDUCTOR DESIGNS

Abstract: an apparatus and method for analyzing dynamic voltage drops in an integrated circuit are disclosed. the method includes providing a gate-level netlist including registers and combinational gates; identifying a first register bus included in a plurality of register buses, the first register bus comprised of one or more of the registers included in the netlist; determining whether a complexity of a first group of combinational gates forming at least one timing path associated with a first bit in the first register bus is less than or equal to a first threshold; assigning the first group of combinational gates to a first group of cells; assigning the first group of cells into a first bus group associated with the first register bus in response to the complexity of the first group of combinational gates being less than or equal to the first threshold; and providing the first bus group to a dynamic voltage drop analysis tool.

Inventor(s): Andrew Paul HOOVER, Shuangjie ZHOU

CPC Classification: G06F30/3323 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models ))

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