TECHNIQUE FOR HANDLING ORDERING CONSTRAINED ACCESS OPERATIONS

Abstract: processing circuitry is provided to perform operations, along with instruction decoder circuitry to decode instructions to control the processing circuitry to perform the operations specified by the instructions. a set of registers is used to hold data values for access by the processing circuitry. the instruction decoder circuitry is responsive to an ordering constrained access instruction used to access multiple data values, and providing register indication information and memory address information, to control the processing circuitry to perform a sequence of access operations, where each access operation causes a data value from amongst the multiple data values to be moved between an associated register determined from the register indication information and an associated memory address determined from the memory address information. further, an ordering indication is derived from the ordering constrained access instruction and used to determine an order in which the multiple data values are to be accessed when performing the sequence of access operations, to thereby ensure that observability conditions required when implementing the ordering constrained access instruction are met.

Inventor(s): Simon John Craske, Jacob Eapen

CPC Classification: G06F9/3013 ({according to data content, e.g. floating-point registers, address registers})

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