20250190139. Accelerated Read Trans (Micron Technology, .)

ACCELERATED READ TRANSLATION PATH IN MEMORY SUB-SYSTEM

Abstract: a system includes a memory device and a processing device coupled to the memory device. the processing device identifies a logical transfer unit (ltu) corresponding to a logical block address (lba) specified by a memory access request. the ltu includes a subset of sequential lbas of a zone of an lba space of the memory device, where one of the subset is the lba. the processing device determines a zone identifier (id) associated with the ltu and retrieves, from a mapping data structure that maps the zone to a subset of a physical address space of the memory device, using the zone id, metadata that specifies a mapping between the ltu identifier and a physical address of the subset of the physical address space. the processing device performs, using the metadata, a memory access operation specified by the memory access request.

Inventor(s): Johnny A. Lam

CPC Classification: G06F3/0655 ({Replication mechanisms})

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