POWER OPTIMIZATION IN ELECTRONIC CIRCUITS BASED ON ROOT CLOCK THROTTLING

Abstract: various example embodiments for supporting power optimizations for electronic circuits are presented. various example embodiments for supporting power optimizations for electronic circuits may be configured to support power optimizations for a block of an electronic circuit. various example embodiments for supporting power optimizations for a block of an electronic circuit may be configured to support a reduction in power consumption by a clock distribution tree of the block of the electronic circuit. various example embodiments for supporting a reduction in power consumption by a clock distribution tree of a block of an electronic circuit may be configured to reduce power consumption by the clock distribution tree of the block of the electronic circuit by supporting root clock throttling for the block of the electronic circuit, based on a workload on the block of the electronic circuit, to reduce power consumption by the clock distribution tree of the block of the electronic circuit.

Inventor(s): Brian Alleyne, Hengwei Hsu, Najeeb Ansari

CPC Classification: G06F1/324 (Means for saving power)

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