20250185363. Forksheet Transistors D (Intel)
FORKSHEET TRANSISTORS WITH DIELECTRIC OR CONDUCTIVE SPINE
Abstract: embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. for example, an integrated circuit structure includes a dielectric spine. a first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. a second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. an n-type gate structure is on the first vertical stack of semiconductor channels, a portion of the n-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. a p-type gate structure is on the second vertical stack of semiconductor channels, a portion of the p-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.
Inventor(s): Seung Hoon SUNG, Cheng-Ying HUANG, Marko RADOSAVLJEVIC, Christopher M. NEUMANN, Susmita GHOSE, Varun MISHRA, Cory WEBER, Stephen M. CEA, Tahir GHANI, Jack T. KAVALIEROS
CPC Classification: H10D86/201 (No explanation available)
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- Patent Applications
- Intel Corporation
- CPC H10D86/201
- Seung Hoon SUNG of Portland OR US
- Cheng-Ying HUANG of Portland OR US
- Marko RADOSAVLJEVIC of Portland OR US
- Christopher M. NEUMANN of Portland OR US
- Susmita GHOSE of Hillsboro OR US
- Varun MISHRA of Hillsboro OR US
- Cory WEBER of Hillsboro OR US
- Stephen M. CEA of Hillsboro OR US
- Tahir GHANI of Portland OR US
- Jack T. KAVALIEROS of Portland OR US