LATCH-UP PREVENTION WITH WELL-TIE EXTENSION USING SELECTIVE WELL DOPING

Abstract: a cmos circuit including a substrate of a first conductivity type with an emitter of a second conductivity type formed on a surface of the substrate, a well tie of the first conductivity type formed between trigger regions and the emitter comprising a strip of heavier doping coupled to a supply-voltage reference, and a well-tie extension including a deep lateral implant of the first conductivity type that overlaps a portion of the well tie. the deep lateral implant may have a degenerate level of doping. the deep lateral implant may be extended to form a guard-ring surrounding the emitter. also, a deep implant of the first conductivity type may be formed at a lower portion of a body of the substrate that overlaps at least a portion of a lower extent of the deep lateral implant. the well tie may be extended to form a deep-profile guard-ring surrounding the emitter.

Inventor(s): Ertugrul Demircan, Douglas Michael Reber, Mehul D. Shroff

CPC Classification: H10D84/854 (No explanation available)

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