Serial Data Receiver with Even/Odd Mismatch Compensation

Abstract: disclosed is a receiver circuit. the receiver circuit is configured to sample, using a recovered clock signal, an equalized signal at times corresponding to odd-numbered data symbols to generate odd samples. the equalized signal is generated based on a plurality of signals that encode a serial data stream that includes a plurality of data symbols having the odd-numbered data symbols and even-numbered data symbols. additionally, the receiver circuit is configured to sample, using the recovered clock signal, the equalized signal at times corresponding to the even-numbered data symbols to generate even samples and to process the odd samples and the even samples to generate a plurality of recovered data symbols.

Inventor(s): Ryan D. Bartling, Jafar Savoj

CPC Classification: H04L7/0029 ({interpolation of received data signal})

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