TUNING OF DATA INTERFACE TIMING BETWEEN CLOCK DOMAINS

Abstract: analog-to-digital converter (adc) circuitry including a delay domain adc that outputs converted analog input data along with a delay domain clock. a clock delay driver outputs a digital domain clock, an early clock leading the digital domain clock signal, and a late clock lagging the digital domain clock. an output latch latches the adc output by the digital domain clock signal. the circuitry includes a timing error detection circuit with inputs receiving the delay domain clock, the early clock, and the late clock. the timing error detection circuit outputs early and late fail flags responsive to detecting timing errors of the digital domain clock relative to the early and late clocks, respectively. timing loop circuitry has an input coupled to the error flag output of the timing error detection circuitry, and an output coupled to a control input of the clock delay driver.

Inventor(s): Eeshan Miglani

CPC Classification: H03K5/14 (PULSE TECHNIQUE (measuring pulse characteristics ; modulating sinusoidal oscillations with pulses ; transmission of digital information ; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation ; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified ; coding, decoding or code conversion, in general ))

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