SEMICONDUCTOR PACKAGE

Abstract: a semiconductor package includes a package substrate including a first waveguide, a pic chip on the package substrate and including a second waveguide, a first molding layer on the package substrate and surrounding the pic chip, an electronic integrated circuit (eic) chip arranged on the first molding layer and the pic chip to vertically overlap both the first molding layer and the pic chip, a semiconductor chip on the pic chip, and a plurality of stack structures arranged horizontally apart from each other on the first molding layer and the pic chip, wherein the first waveguide is disposed on an upper surface of the package substrate, and wherein the pic chip is arranged on the package substrate such that a surface of the pic chip, adjacent to the second waveguide, faces the package substrate.

Inventor(s): Hyunsoo Chung, Inyoung Lee

CPC Classification: H01L25/167 (the devices being of types provided for in two or more different main groups of groups - , or in a single subclass of , , e.g. forming hybrid circuits)

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