SEMICONDUCTOR DEVICES AND SYSTEMS INCLUDING STACKED LOGIC DIES

Abstract: a semiconductor device includes a first logic die comprising: a clock source configured to generate a clock signal; and a first clock mesh for receiving the clock signal from the clock source. the device includes a second logic die stacked over the first logic die, the second logic die comprising: a second clock mesh for receiving the clock signal from the clock source. the device includes a plurality of conductive connections between the first clock mesh and the second clock mesh to transmit the clock signal from the first clock mesh to the second clock mesh. various other methods and systems are also disclosed.

Inventor(s): Russell Schreiber, John Wuu, Spence Oliver

CPC Classification: H01L25/0652 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (use of semiconductor devices for measuring ; resistors in general ; magnets, inductors or transformers ; capacitors in general ; electrolytic devices ; batteries or accumulators ; waveguides, resonators or lines of the waveguide type ; line connectors or current collectors ; stimulated-emission devices ; electromechanical resonators ; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers ; electric light sources in general ; printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components ; use of semiconductor devices in circuits having a particular application, see the subclass for the application))

Search for rejections for patent application number 20250183226