20250183192. Passivation Scheme Design Wafer Singulat (Taiwan Semiconductor Manufacturing , .)

PASSIVATION SCHEME DESIGN FOR WAFER SINGULATION

Abstract: a method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.

Inventor(s): Hsien-Wei Chen, Ying-Ju Chen, Ming-Fa Chen

CPC Classification: H01L23/544 (Marks applied to semiconductor devices {or parts}, e.g. registration marks, {alignment structures, wafer maps (test patterns for characterising or monitoring manufacturing processes )})

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