SEMICONDUCTOR PACKAGE

Abstract: provided is a semiconductor package including stacked semiconductor chips. respective ones of the semiconductor chips include a substrate having front and rear surfaces, an interlayer dielectric layer on the front surface of the substrate, a lower protection layer on a bottom surface of the interlayer dielectric layer, lower conductive pads in the lower protection layer, an upper protection layer on the rear surface of the substrate, and upper conductive pads in the upper protection layer. the upper conductive pads of a first one of the semiconductor chips are respectively in contact with the lower conductive pads of an adjacent one of the semiconductor chips. each of the upper protection layer and the lower protection layer has a non-uniform thickness. ones of the lower conductive pads have respective thicknesses that are different from each other.

Inventor(s): Won Il Lee, Hyungchul Shin, Enbin Jo

CPC Classification: H01L23/5283 ({Geometry or} layout of the interconnection structure {( takes precedence; algorithms )})

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