METHODS FOR IMPROVING DEPTH LOADING IN TRANSISTORS

Abstract: method for reducing the depth loading of dielectric structures on a substrate are disclosed. the substrate includes a set of isolated long dummy gate regions and a set of dense long dummy gate regions. each dummy gate region is surrounded on each lateral side by a dielectric spacer and a continuous etch stop layer. a hard mask layer is formed over the substrate to exert a force that reduces stresses within the substrate. each dummy gate is then etched to form an isolation volume and a trench in the substrate, and then filled with dielectric material to form a dielectric structure. the depth loading, or the difference in trench depths between the set of isolated long dielectric structures and the set of dense short dielectric structures, is thus reduced.

Inventor(s): Tzu-Ging Lin, Jun-Ye Liu, Chun-Liang Lai, Ai Hsuan Lee, Yun-Chen Wu

CPC Classification: H01L21/76229 (Dielectric regions {, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers})

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