MEMORY DEVICE AND PROGRAM OPERATION THEREOF

Abstract: in certain aspects, a memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. at least one of the memory cells is set to one of 2levels corresponding to a piece of n-bits data, where nis an integer greater than 1. the peripheral circuit is configured to apply a first program voltage to a word line of the memory cells, perform a first verification of the word line of the memory cells at a last level of the 2levels after applying the first program voltage, perform a first verify fail count (vfc) based on a result of the first verification and a first vfc criterion, apply a second program voltage greater than the first program voltage to the first word line of the memory cells after performing the first vfc, and perform a second vfc based on the result of the first verification and a second vfc criterion different from the first vfc criterion within a period of applying the second program voltage.

Inventor(s): Weijun Wan

CPC Classification: G11C16/3459 ({Circuits or methods to verify correct programming of nonvolatile memory cells})

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