SEMICONDUCTOR MEMORY DEVICE

Abstract: a semiconductor memory device includes: a first pull-down n-channel mos transistor that includes: a drain connected to a word line; a source connected to a ground line; and a gate connected to a first node; a first series connection n-channel mos transistor that includes: a drain connected to a power supply line; and a source connected to the first node; and a second series connection n-channel mos transistor that includes: a drain connected to the first node; and a source connected to the ground line. the inverse-logic signal of a signal to be input to the gate of the second series connection n-channel mos transistor is input to the gate of the first series connection n-channel mos transistor.

Inventor(s): Atsushi MOTOTANI

CPC Classification: G11C11/418 (forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger)

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