SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

Abstract: a memory system includes a plurality of memory devices, each connected to internal channels respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller connected to an external channel including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit connecting the external channel to each of the internal channels. the interface circuit is configured to perform channel conversion by serializing a parallel data signal received from the controller through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.

Inventor(s): Youngmin Jo, Tongsung Kim, Chiweon Yoon, Byunghoon Jeong

CPC Classification: G11C7/1087 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers)

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