MEMORY SYSTEMS WITH VERTICAL INTEGRATION

Abstract: a memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. the memory device includes a second layer disposed with respect to the first layer in a vertical direction. the second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. the memory device includes a plurality of interconnect structures extending along the vertical direction. at least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

Inventor(s): Chieh Lee, Yi-Ching Liu, Chia-En Huang, Jen-Yuan Chang, Yih Wang

CPC Classification: G11C5/06 (STATIC STORES (semiconductor memory devices ))

Search for rejections for patent application number 20250182796