20250182718. Reducing 3d Lookup Table (ATI Technologies ULC)

REDUCING 3D LOOKUP TABLE INTERPOLATION ERROR WHILE MINIMIZING ON-CHIP STORAGE

Abstract: systems, apparatuses, and methods for reducing three dimensional (3d) lookup table (lut) interpolation error while minimizing on-chip storage are disclosed. a processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3d representation of the pixel component space. for example, in one implementation, the processor calculates mappings for 17�17�17 vertices within the 3d representation. other implementations can include other numbers of vertices. rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3d representation of the first gamut. this results in a smaller increase to the lut size as compared to increasing the number of vertices. the centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.

Inventor(s): Keith Lee, David I. J. Glen, Jie Zhou, Yuxin Chen

CPC Classification: G09G5/06 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays ; static indicating arrangements comprising an association of a number of separate sources or light control cells ; static indicating arrangements comprising integral associations of a number of light sources , , , ; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof ))

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