20250182235. Processor Hav (Imagination Technologies Limited)

PROCESSOR HAVING FIRST AND SECOND PIPELINES AND BLOCKING CIRCUIT ENABLING SECOND PIPELINE TO PROCESS TASKS DURING DEALLOCATION OF MEMORY ALLOCATED TO FIRST PIPELINE

Abstract: a processor includes a first processing pipeline, a second processing pipeline and a memory management that allocates memory regions from memory for the first processing pipeline to write the data of each of a first of a sequence of tasks, and deallocates each of the memory regions after the data therein has been processed by the second processing pipeline. a blocking circuit enables the second processing pipeline to start processing a second sequence of tasks while the memory management circuit is still deallocating some of the memory regions allocated to the data portions of the first of said sequence of tasks, the blocking circuit preventing identifiers of the data portions of the second task being passed to the memory management circuit until the memory management circuit indicates that it has completed deallocating the memory regions allocated to all the data portions of the first task.

Inventor(s): Michael John Livesley, Ian King, Alistair Goudie

CPC Classification: G06T1/20 (Processor architectures; Processor configuration, e.g. pipelining)

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