20250181809. Op (INTERNATIONAL BUSINESS MACHINES)
OPTIMIZING THE ERROR CHECKING LOGIC IN A PROCESSOR
Abstract: an approach for optimizing error-checking logic in a processor design is disclosed. the approach includes performing a static analysis on the processor design, wherein the processor design includes one or more latches and one or more checkers and generating a bipartite graph mapping between the one or more latches and the one or more checkers. the approach also determines checker set cover based on the mapping and preselecting timing critical checkers. the approach also determines redundant checkers based on checker activity and eliminate redundant checkers. finally, the approach determines whether convergence criteria has been met.
Inventor(s): Karthik V. Swaminathan, Douglas Balazich, Ramon Bertran Monfort, Arvind Haran, Alper Buyuktosunoglu, Hans Mikael Jacobson, Matthias Pflanz, Pradip Bose
CPC Classification: G06F30/3315 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models ))
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- Patent Applications
- INTERNATIONAL BUSINESS MACHINES CORPORATION
- CPC G06F30/3315
- Karthik V. Swaminathan of Mount Kisco NY US
- Douglas Balazich of Poughkeepsie NY US
- Ramon Bertran Monfort of New Orleans LA US
- Arvind Haran of Liberty Hill TX US
- Alper Buyuktosunoglu of White Plains NY US
- Hans Mikael Jacobson of White Plains NY US
- Matthias Pflanz of Holzgerlingen DE
- Pradip Bose of Yorktown Heights NY US