EFFICIENT INTEGRATED CIRCUIT SIMULATION AND TESTING

Abstract: a method comprising using at least one hardware processor for: running a monte carlo simulation of possible integrated circuit (ic) process variations of each of a plurality of ic cell types, wherein each of the plurality of ic cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the monte carlo simulation, creating a library of ic cell types and their corresponding behavioral values for each of the possible ic process variations, and storing the library in a non-transient memory; receiving an ic design embodied as a digital file; correlating the received ic design with the library; and predicting a frequency distribution and a power distribution of ics manufactured according to the ic design.

Inventor(s): Evelyn LANDMAN, Yair TALKER, Eyal FAYNEH, Yahel DAVID, Shai COHEN, Inbar WEINTROB

CPC Classification: G06F30/3312 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models ))

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