LOAD MANAGEMENT ARCHITECTURE FOR ARTIFICIAL INTELLIGENCE (AI) ACCELERATION

Abstract: a device comprising an accelerator is disclosed. an interface may receive a frequency control signal from a processor. a control circuit may set a frequency of a circuit based at least in part on the frequency control signal from the processor. the circuit may process data based at least in part on a data processing command from the processor.

Inventor(s): Donny YI

CPC Classification: G06F13/4291 (Bus transfer protocol, e.g. handshake; Synchronisation)

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