CONCURRENT SUPPORT FOR MULTIPLE CACHE INCLUSIVITY SCHEMES USING LOW PRIORITY EVICT OPERATIONS

Abstract: systems and methods are disclosed for concurrent support for multiple cache inclusivity schemes using low priority evict operations. for example, some methods may include, receiving a first eviction message having a lower priority than probe messages from a first inner cache; receiving a second eviction message having a higher priority than probe messages from a second inner cache; transmitting a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in a cache hierarchy; and, transmitting a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.

Inventor(s): Wesley Terpstra, Richard Van, Eric Andrew Gouldey

CPC Classification: G06F12/121 (Replacement control)

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