20250181496. Logical Block Address (Micron Technology, .)

LOGICAL BLOCK ADDRESS STATUS IDENTIFICATION

Abstract: implementations described herein relate to logical block address status identification. in some implementations, a processing device may send, and a memory device may receive, a command that includes at least a first argument and a second argument. the first argument may indicate a logical block address start value and the second argument may indicate a logical block address range value. the memory device may send, and the processing device may receive, a packet that includes a list of logical block addresses and that indicates, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid. the processing device may identify a mismatch between a valid logical block address and a corresponding file system entry, and may send, to the memory device, an erase command that indicates to erase the valid logical block address.

Inventor(s): Gianluca COPPOLA, Marco DI PASQUA

CPC Classification: G06F12/0246 ({in block erasable memory, e.g. flash memory})

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