Hardware Test Mode for Processor Core

Abstract: systems and methods are disclosed for implementing a hardware test mode for a processor core. for example, some methods may include writing to one or more test mode registers to change a microarchitectural state of a processor core from a first state to one or more test mode states; executing a sequence of instructions on the processor core in the one or more test mode states to obtain a resulting architectural state of the processor core; comparing the resulting architectural state to an expected architectural state associated with the sequence of instructions to obtain a test result; and writing to the one or more test mode registers to restore the microarchitectural state of the processor core to the first state.

Inventor(s): Monia Chiavacci, Robin Randhawa, Trefor Southwell

CPC Classification: G06F11/263 (Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers})

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