MEMORY CONTROLLERS AND MEMORY SYSTEMS

Abstract: a memory controller to control a memory module including data chips and a parity chip, includes an error correction code (ecc) engine. the ecc engine includes an ecc decoder to perform a first ecc decoding to correct a symbol error in a read codeword set and perform a second ecc decoding to correct multi-bit error and to detect triple-bit error in the read codeword set in parallel with performing the first ecc decoding. the ecc decoder generates a syndrome including a first sub syndrome, a second sub syndrome and a third sub syndrome, corrects the symbol error, and corrects the multi-bit error and detect the triple bit error.

Inventor(s): Jiho Kim, Changkyu Seol, Hyunjung Ko, Sungrae Kim, Seonghyeog Choi

CPC Classification: G06F11/1044 ({with specific ECC/EDC distribution})

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