ASYNCHRONOUS DATA TRANSFER

Abstract: an apparatus is provided with asynchronous boundary transfer circuitry to transfer data across a clock domain boundary. the asynchronous boundary transfer circuitry has buffer circuitry with buffer storage elements, and source and sink synchronisation circuitry to control the transfer of the data. to initiate a transfer of data items, the source synchronisation circuitry sends a transfer request to the sink synchronisation circuitry indicating that the data items have been stored in one or more buffer storage elements and encoding an indication of one or more elements of destination circuitry targeted by the data items. the sink synchronisation circuitry is responsive to a transfer request to decode an indication of the elements of destination circuitry targeted by the data items, provide incoming data item notifications to elements of destination circuitry, and allow the data items to be read from buffer storage elements indicated by the given transfer request.

Inventor(s): Alex James WAUGH

CPC Classification: G06F5/06 (for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor ( takes precedence)})

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