FIN TRIM PLUG STRUCTURES HAVING AN OXIDATION CATALYST LAYER SURROUNDED BY A RECESSED DIELECTRIC MATERIAL

Abstract: fin trim plug structures for imparting channel stress are described. in an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. the fin has a trench separating a first fin portion and a second fin portion. a first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. a second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. an isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. the isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

Inventor(s): Leonard GULER, Nick LINDERT, Biswajeet GUHA, Swaminathan SIVAKUMAR, Tahir GHANI

CPC Classification: H10D30/798 (No explanation available)

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