SEMICONDUCTOR PROCESSING INTEGRATION FOR BIPOLAR JUNCTION TRANSISTOR (BJT)

Abstract: the present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (bjt). in an example, a semiconductor device includes a semiconductor substrate, a pedestal dielectric layer, a collector layer, a base layer, and an emitter layer. the semiconductor substrate includes a bipolar junction transistor region. the pedestal dielectric layer is in the bipolar junction transistor region and is over an upper surface of the semiconductor substrate. the collector layer is on the upper surface of the semiconductor substrate and is through the pedestal dielectric layer. the base layer is on the collector layer and an upper surface of the pedestal dielectric layer. the pedestal dielectric layer extends laterally over the upper surface of the semiconductor substrate from the base layer. the emitter layer is on the base layer.

Inventor(s): Hiroshi Yasuda, Jonathan Lane, Giulio Albini, Michael Todd, Robert Cassel

CPC Classification: H10D10/821 (No explanation available)

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