Systems, Methods, and Devices for a Wordline or a Bitline Formed and Disposed Within a Backside Metal Layer

Abstract: according to one implementation of the present disclosure, an integrated circuit comprises: a memory macro unit including: one or more bitcells of one or more bitcell arrays, where a wordline or a bitline is at least partially disposed within a backside metal layer of the memory macro unit. in one implementation, a method comprises: transmitting, by a first wire of wiring, one or more control signals, where the first wire is disposed at least partially within a back-side metal layer. in one implementation, an integrated circuit comprises: a wire configured to transmit one or more control signals, where the wire is disposed at least partially on a back-side metal layer.

Inventor(s): Andy Wangkun Chen, Yew Keong Chong, Sriram Thyagarajan, Vivek Asthana

CPC Classification: H10B10/12 (ELECTRONIC MEMORY DEVICES)

Search for rejections for patent application number 20250176152