WIRELESS TRANSMITTER WITH IMPROVED DATA RATE

Abstract: this disclosure is directed to a transmitter including a phase locked loop (pll), a modulator, and a power amplifier (pa). a controller including programmable and/or hardened logic circuitry may be coupled to the pll and the modulator. the controller may provide encoded signals based on quadrature phase shift keying (qpsk) scheme for transmission by the transmitter. in particular, the controller may provide multiple bursts of pulses indicative of data packets to the modulator. moreover, the controller may provide instructions indicative of generating clock signals with in-phase and quadrature phases to the pll. the pll may generate clock signals corresponding to the in-phase and quadrature phases. as such, the transmitter may generate in-phase and quadrature output signals based on receiving each burst of pulses with either in-phase or quadrature phases.

Inventor(s): Christian Venerus, Utku Seckin, Vikram Magoon

CPC Classification: H03L7/093 (using special filtering or amplification characteristics in the loop ( - take precedence))

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