MULTIPHASE CLOCK SIGNAL GENERATING CIRCUIT AND EYE DIAGRAM GENERATING CIRCUIT

Abstract: a multi-phase clock signal generating circuit, configured to generate a plurality of output clock signals with different phases, comprising: a charge pump, configured to generate a control voltage according to a reference clock signal and a target clock signal; a delay circuit, comprising a delay chain with a plurality of delay units, configured to generate a plurality of candidate clock signals and the target clock signal according to the control voltage; and a phase selecting circuit, configured to select at least two of the candidate clock signals as the output signals.

Inventor(s): Tse-Hung Chen

CPC Classification: H03K5/133 (Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals)

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