LOAD LOCK ARRANGEMENTS CONFIGURED FOR PERFORMING PARALLEL PROCESSES, AND ASSOCIATED SYSTEMS AND METHODS

Abstract: load lock arrangements, semiconductor processing systems including such load lock arrangements, and associated methods for performing parallel processes within such load lock arrangement are disclosed. the load lock arrangements disclosed include an alignment assembly disposed within a load lock body and configured for aligning a substrate within the interior of the load lock body while in parallel reducing the pressure within the load lock body.

Inventor(s): Salam Harb, Samer Banna, Pradeep Nambiath

CPC Classification: H01L21/68 (for positioning, orientation or alignment)

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