TOOL FOR FAULT DETECTION AND CLASSIFICATION IN DESIGN AND GENERATION OF NETWORK-ON-CHIP (NoCs)

Abstract: system and methods are implemented by a tool used in generation and synthesis of networks, such as a network-on-chip (noc). the tool includes an algorithm that identifies and classifies faults and thereby results in efficiency in determination of the cause of the fault. the tool allows a designer or user to provide solutions or make edits as needed to address the cause of the fault.

Inventor(s): Xavier VAN RUYMBEKE, Amir CHARIF, Christopher PEZLEY

CPC Classification: G11C29/44 (STATIC STORES (semiconductor memory devices ))

Search for rejections for patent application number 20250174294