Memory apparatus having at-speed test mechanism and memory test method of the same

Abstract: the present disclosure discloses a memory apparatus having at-speed test mechanism. an output function circuit block receives an output signal from a memory circuit to generate an output result. a signal feeding circuit block includes a feeding flip-flop circuit, a feeding logic circuit and a feeding multiplexer. the feeding flip-flop circuit receives and outputs a feeding signal. the feeding logic circuit receives and processes the feeding signal to generate a processed control signal. the feeding multiplexer is electrically coupled to the feeding flip-flop circuit and the feeding logic circuit. in an at-speed test mode, a test pattern is written to the memory circuit and the feeding multiplexer selects the feeding signal to be a feeding control signal to operate the memory circuit to directly control the memory circuit to output the test pattern in the output signal such that the output result is verified to perform an output at-speed test.

Inventor(s): YU-CHENG LO, CHUN-YI KUO

CPC Classification: G11C29/10 (STATIC STORES (semiconductor memory devices ))

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